Analog Circuit Design: Smart Data Converters, Filters on by Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

By Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

Analog Circuit layout includes the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and necessary layout rules within the zone of analog circuit layout. each one half is gifted by means of six specialists in that box and cutting-edge details is shared and overviewed. This publication is quantity 18 during this winning sequence of Analog Circuit layout, offering useful details and perfect overviews of: shrewdpermanent facts Converters: Chaired by means of Prof. Arthur van Roermund, Eindhoven college of expertise, Filters on Chip: Chaired by way of Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired through Prof. M. Steyaert, Catholic college Leuven, Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the academic insurance additionally makes it appropriate to be used in a complicated layout.

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Extra resources for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters

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3 First Block Diagram The block diagram of this initial charge-sharing SAR ADC architecture is shown in Fig. 7. g. e. – generate the control signals for the S&H switches – generate the signal precharge 48 J. N–1] Fig. 7 Block diagram of initial charge-sharing SAR architecture – go through a loop that for every bit of the ADC • activate the comparator • interprete the result and close one of the switches cp or cn – output the digital code that represents the digitized value of the input voltage.

Comparator-based switched-capacitor circuits for scaled CMOS technologies. IEEE J. Solid-State Circuits 41(12), 2658–2668 (2006) 49. J. , A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration, in Symposium of VLSI Circuits Digest, Honolulu, HI, USA, June 2010, pp. 237–238 50. B. E. Boser, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J. Solid-State Circuits 38(12), 2040–2050 (2003) 51. Ding-Lan Shen and Tai-Cheng Lee, A 6-Bit 800-MS/s pipelined A/D converter with open-loop amplifiers, in Symposium on VLSI Circuits Digest, June 2006, pp.

V. 2012 39 40 J. Craninckx QX = –2CVIN VX = 0 VX + VC – C C 2 C 8 C 4 C 16 VIN C 16 VREF Fig. 1 Conceptual 5-bit charge-redistribution SAR ADC [1] divider constructed between the capacitors. A full conversion cycle thus consists out of 1 C N events (1 input sampling and N comparisons). This conceptual ADC schematic is deceivingly simple: there is only one active element (a comparator) and it further contains just some passive capacitors and a set of switches. An easy conclusion would be that a really low power consumption can be obtained.

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